| Abstract |
| Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - 30 μm in diameter and 60 μm in depth with 200 μm pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. SiO2, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time. |
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| Key Words |
| three dimensional packaging, electrical, electronic, plating, electrochemistry, scanning electron microscopy, SEM |
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